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Digital Design Engineer

Job in Walnut Creek, Contra Costa County, California, 94598, USA
Listing for: 1010 Analog Devices Inc.
Full Time position
Listed on 2026-03-07
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™.

Learn more at  and on Linked In and Twitter (X) .

Job Description:

The Edinburgh team is seeking a Principal Digital Design Engineer to grow its talented group located in San Jose, U.S.A . ADI’s Personal Electronics Solutions Group has been leading the industry, working with the world’s leading consumer companies, providing high value audio solutions for the portable, wearable, and gaming markets. We are poised for significant growth as we enter the next phase, driven by the insatiable consumer demand for new technologies and access to information.

The successful candidate will join a diverse team that is motivated, supportive, and eager to share its knowledge. It is the ideal place to enhance both technical expertise and interpersonal skills, whilst collaborating with our design teams worldwide.

Responsibilities and Duties include but not limited to:
  • Be r esponsib le for the architecture, design, emulation, and verification of the digital portion of Analog Devices audio products
  • Drive improvements in new product cycle time, design quality, design methodology and engineering productivity
  • Collaborate with internal stakeholders and customers to ensure future products meet the demands of the market
  • Work closely with support organizations to ensure suitable design, verification, and emulation tools are available and utilized
  • Initiate innovation and continuous improvement. Run feasibility studies and innovation
  • Use latest EDA tools to continually improve quality and design cycles
  • Lead design projects with estimation, planning, tracking and QA to ensure accomplishing design goals
  • Verif y complex System-on-Chip (SoC) solutions with exposure to advanced methodologies such as UVM
  • Work with the Analog design team and chip lead to identify partitioning and block requirements
  • Support DFT strategy and implementation
  • Mentor junior design engineers within the group. Support customer, vendor foundry
  • Collaborate with other designers and layout team members to integrate the digital blocks into the chip top level
  • Perform the chip level verification before the tape out process
  • Conduct circuit design reviews before taping out
  • Perform silicon wake up and debug . Generate production test vectors, support test development and ramp to production
  • Support the ATE team to develop an automated test solution and the application team to enable final products.
Minimum Qualifications:
  • MSEE + minimum 1 5+ years of relevant experience or BSEE + 20 years relevant experience in Semiconductor industry doing digital standard cell-based IC design using Verilog, perform ing Linting/CDC/RDC checks, synthesis, timing analysis , PnR , power analysis and physical verification tools
  • Demonstrated Experience (“DE”) developing digital front end circuit architecture, designing consumer products, integrating micro-processors such as RISC-V, and modeling signal processing hardware utilizing MATLAB and Simulink
  • Utilize abstract design models such as Register Transfer Level (RTL) to design and verify signal processing blocks, clock control managers, and finite state machines
  • Strong t rack record of development products in volume production including design lead roles
  • Experience with design for testability, scan insertion, scan pattern debugging
  • Familiarity with Cadence and Synopsys design tools
  • DE verifying digital designs using Universal Verification Methodology (UVM), System Verilog (SV) Assertions, Formal verification Techniques and Verification IP (VIP) development
  • Experience debugging ICs and associated evaluation systems in a lab environment
  • Excellent communication skills, ability to work within a cross functional team…
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