SoC Physical Design Engineer, PnR

We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance u0026 low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.

* You will be responsible for all aspects of physical design implementation from RTL2

GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.

- You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.

- You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area u0026 power optimization etc.

Knowledgeable in partition level Pu0026R implementation including floor planning, clock u0026 power distribution, timing closure, and physical u0026 electrical verification. Knowledge of PD construction u0026 analysis flows and methodology. Strong interpersonal skills. Recent successful tapeouts in deep submicron technology.

Experience with large SOC designs (u003e20M gates) with frequencies in excess of 1

GHZ. Shown ability to execute to stringent schedule u0026 die size requirements. Experienced in industry standard tools and understanding their capabilities and underlying algorithms.

Minimum BS and 3+ years of relevant industry experience.