_Engineer: Pre-Silicon Functional Validation - III

Job Title

Your responsibility will include but not be limited to:
Validating designs at the full-chip level by authoring validation plans, writing focus tests, creating templates defining coverage strategies, developing and analyzing coverage monitors, creating event injectors, writing architectural and micro-architectural correctness checkers, developing BFMs (Bus Functional Model), running functional simulations, and debugging failures. Maintaining and enhancing the validation infrastructure by creating new tools to support validation.

Possess a Bachelor's or Master's degree in Electrical Engineering and/or Computer Engineering and/or Computer Science with 8+ years of experience in the area of either hardware design or verification. 5+ years of pre-silicon verification work using a validation methodology such as UVM/OVM. In-depth understanding of logic design and validation methodologies. Strong competency in Verilog and/or System Virology. Substantial experience working with VCS or other 3rd party simulators.

Substantial experience in defining validation plans and writing test benches per architecture spec. Strong written/verbal communication skills.

In-depth understanding of logic design and validation methodologies. Verilog and/or System Verilog. UVM / OVM. Substantial experience working with VCS or other 3rd party simulators. Substantial experience in defining validation plans and writing test benches per architecture spec.