Staff, RTL Engineer

Staff, RTL Engineer at Tenstorrent.

Location:

United States;
New Taipei City, Taiwan

Engagement:
Remote

• Design and implement RTL for digital subsystems, fabrics, and SoC-level integrations.
• Manage microarchitecture development while balancing power, performance, and area requirements.
• Collaborate with architecture, verification, physical design, and DFx teams.
• Perform pre-silicon and post-silicon debugging, including silicon bring-up and root-cause analysis.
• Contribute to the full silicon lifecycle from initial concept to final production.

• Bachelor, Master, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• Minimum 5 years of professional experience in ASIC, SoC, or chiplet development.
• Proficiency in Verilog-based design and industry-standard simulation and synthesis tools.
• Expertise in digital subsystem integration and protocols including AXI, AHB, APB, I3C, and SPI.
• Ability to solve complex logic and system-level design challenges.

• Experience with RISC-V CPU cores.
• Familiarity with DFT/DFD methodologies such as scan test, MBIST, JTAG, and ATPG.
• Background in open-source hardware projects.
• Knowledge of chip-level debug architectures.

• Verilog
• AXI, AHB, APB, I3C, SPI
• DFT/DFD (Scan, MBIST, JTAG, ATPG)
• Simulation and synthesis tools

Compensation ranges from $100k to $500k, including base salary and variable components, determined by experience, education, and location.

Employment is contingent upon the candidate being eligible to access U.S. export-controlled technology. Offers may require citizenship, permanent residency, or a license from the U.S. Commerce Department due to export control regulations. Candidates will be assessed for the appropriate seniority level during the interview process.