ASIC Physical Design Engineer - DFT, Senior

Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon.

In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market.

Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.

As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon, not a coordination role.

Hands-on DFT Implementation

• Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
• Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
• Work directly in RTL, synthesis, and DFT tool flows.
• Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
• Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.

Partner with Physical Design

• Work closely with backend implementation teams to ensure successful physical realization of the DFT architecture.
• Guide scan chain partitioning, compression planning, and test clock architecture.
• Address power-aware test implementation, timing closure considerations, and test mode integration.

Cross-Functional Execution

• Partner closely with RTL design, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT solutions are correct, compliant, complete, and consistent through silicon bring-up.

AI-Enabled Engineering

• Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG and coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.

• A BS, MS, or PhD in Electrical Engineering or Computer Engineering.
• 8+ years of ASIC development experience.
• Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts.
• Deep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis.
• Hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required.
• Practical experience with synthesis and gate-level verification.
• Strong scripting ability in Python, Tcl, Perl, or similar languages.
• Excellent debugging skills across RTL, netlists, and silicon failure analysis.
• A demonstrated ability to drive technical execution across cross-functional engineering teams.

• Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures.
• Exposure to high-speed Ser Des and advanced process nodes (5nm and below).
• Background in low-power design, yield enhancement methodologies, and manufacturing test optimization.
• Hands-on experience with silicon bring-up, failure analysis, and post-silicon debug.
• A solid grasp of secure manufacturing and DFT, including the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management,…