ASIC Design Engineer

Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon.

In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market.

Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.

As an ASIC Design Engineer, you will help design, implement, and deliver IP blocks and subsystems for Positron.ai's inference ASICs/SoCs. Working under the guidance of senior engineers, you will write and verify System Verilog RTL, take ownership of well-scoped blocks, and learn the full front-end flow from microarchitecture through RTL signoff. You'll collaborate closely with architecture, verification, and physical design teams, building deep hands-on experience with high-performance silicon while growing toward greater technical ownership.

• Implement clean, parameterized System Verilog RTL for assigned blocks based on microarchitecture specs developed with senior engineers.
• Contribute to microarchitecture documentation and help define block-level interfaces.
• Add embedded assertions and follow team guidelines for clocking, resets, and power intent.

• Run and debug lint, CDC/RDC, and synthesis checks on your blocks, and resolve issues with support from the team.
• Help with timing analysis and work with PD on block-level timing fixes.
• Track and report PPA metrics for your blocks, and propose optimizations.

• Support integration of standard interfaces and IP (e.g., AMBA AXI, DMA engines, memory controllers).
• Learn and apply protocol requirements for high-performance interconnects and memory interfaces.
• Follow established coding guidelines, IP packaging standards, and signoff checklists.
• Write and maintain scripts (Python/Tcl/Make) that improve design flows and team productivity.

• Work with Verification to review test plans, debug failures, and close coverage on your blocks.
• Help correlate RTL behavior against architecture and performance models.
• Take part in bring-up and post-silicon debug activities as needed.

• Take part in design reviews, present your work, and incorporate feedback.
• Build expertise in microarchitecture tradeoffs through mentorship from senior engineers.

• BS/MS in EE/CE (or related field) with 0–3 years of ASIC/SoC RTL design experience (internships and relevant graduate research count).
• Solid working knowledge of System Verilog/Verilog for synthesizable RTL design.
• Understanding of digital design fundamentals: clocking, resets, pipelining, FSMs, FIFOs, and clock domain crossing.
• Exposure to front-end tools and flows (simulation, lint, synthesis, or STA) from industry or academic projects.
• Familiarity with at least one of: AMBA AXI/AHB/APB, DDR/HBM, PCIe, cache/memory hierarchies, or datapath design.
• Scripting ability in Python, Tcl, or similar.
• Strong problem-solving skills, eagerness to learn, and clear written and verbal…