Physical Design Manager; Semiconductor Domain

We are looking for a Physical Design Manager who will operate in a hands-on, execution-first player-coach role. This position combines direct technical contribution with first-line people leadership. The ideal candidate is someone who wants to stay deeply involved in physical design and timing closure while guiding a small team through critical execution phases. This is not a pure people-management role. Success in this position is measured by delivery, convergence, and technical ownership, not by team size.

Responsibilities

• Serve as the primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems
• Perform hands-on physical design and timing analysis, including late-stage debug and convergence
• Define and actively drive closure strategy, not just review results
• Act as a key technical escalation point, stepping in directly when progress stalls
• Lead and mentor a small team of PD engineers as a player-coach
• Provide prioritization, technical direction, and day-to-day execution guidance
• Coordinate closely with STA, RTL, CAD, and Program teams to resolve complex issues
• Support hiring, onboarding, and ramp-up of new team members while maintaining technical ownership
• Communicate execution status, risks, and tradeoffs clearly to engineering leadership

Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10–15 years of related professional experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5–10 years of experience; or equivalent professional experience in lieu of a formal degree.

Required Skills

• Principal-level physical design expertise with a proven track record delivering timing-closed ASICs or complex So Cs
• Demonstrated success in timing analysis and closure across multiple designs
• Deep understanding of advanced timing concepts including SI, CDC, LVF, POCV, and related methodologies
• Strong proficiency with PD and STA tools (e.g., Synopsys Prime Time or equivalent), scripting, and UNIX/Linux environments
• Strong written and verbal communication skills with the ability to articulate technical tradeoffs
• Experience leading PD engineers in a first-line, hands-on capacity
• Proven ability to operate as a player-coach, contributing technically while guiding others
• Experience mentoring engineers and developing PD talent through active engagement
• Ability to coordinate execution across cross-functional teams with clear ownership and accountability

Preferred Skills

• Experience owning full-chip or large-subsystem PD and timing closure.
• Familiarity with timing methodology and flow development.
• Experience working with multi-site or globally distributed teams.
• Experience balancing FTE and contractor resources.