Physical Design Engineer

Position Overview

NVIDIA is seeking Senior Physical Design Engineers to join our Networking Silicon engineering team, developing high‑speed communication devices.

• Lead all aspects of physical design and implementation of SOC devices targeting the networking markets.
• Work at the partition level, establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
• Perform daily activities across the physical chip development life cycle (RTL‑to‑GDS), including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

• BSEE / MSEE or equivalent.
• At least 3+ years of experience in VLSI physical design implementation on 5nm, 4nm, and 3nm technologies.
• Strong experience with design flow development, debugging, and ML/AI solutions implementation.
• Validated expertise as a power user of P&R, timing analysis, physical verification, IR drop analysis, and CAD tools from Synopsys and Cadence.
• Proficiency in scripting with Python, Perl, Tcl, and Make is helpful.

Base salary range is $116,000–$189,750 for Level2 and $136,000–$218,500 for Level
3. Candidates will also be eligible for equity and other benefits.

NVIDIA is an equal‑opportunity employer and is committed to fostering an inclusive work environment. NVIDIA does not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.