Physical Design Engineer

What You’ll Be Doing

• You will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
• You will work at the partition level.
• As a member of a team, you will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
• Your daily work involves all aspects of physical chip development (RTL2
  
  GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.

• BSEE / MSEE or equivalent experience.
• 3+ years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
• Able to assist in design flow development and debugging, including application of ML/AI solutions.
• Strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
• Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/route and tapeout solutions.
• Strong analytical and debugging skills.
• Proficiency using Python, Perl, Tcl, Make scripting is helpful.
• Great teammate.

Your base salary will be determined based on your location, experience, and compensation for similar positions. The base salary range is $116,000 – $189,750 for Level 2, and $136,000 – $218,500 for Level 3. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.