Design Verification Engineer

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This range is provided by SPECTRAFORCE. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

$80.00/hr - $90.00/hr

Remote

Job Description

• Work with researchers and architects defining verification plans for each of the different core IP.
• Define and track detailed test plans for the different modules and top levels.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Summary

• Design verification Engineer with 5+ years of hands-on experience in Verilog, System Verilog, C/C++ based verification and UVM methodology.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Key Projects/Day-to-Day Responsibilities:

• Work with researchers and architects defining verification plans for each of the different core IP.
• Define and track detailed test plans for the different modules and top levels.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Purpose/Size of this team & where does this position fit within the team?

• The team has about 8-9 individuals, this individual will be working directly with the manager.

How will performance be measured?

• Will basically be measured on the tasks and projects given and the delivery of these too. Being able to complete on time as per the deadlines.

What makes this role interesting?

• This team is currently working in the Reality Lab space within the AR/VR world and creating the graphics for them. Client has been seen as an industry leader in this space and the exposure and learning potential is great.

Must-Have Skills:

• Hands-on experience in Verilog, System Verilog (engineering).
• C/C++ based verification and UVM methodology.
• Experience writing python scripts.

Nice-to-have Skills:

• Ability to write from scratch UVM methods.
• Simulation or relation experience.
• Experience from Bay Area/Silicon/Product Delivery Companies.

Years of Experience:

• Minimum 5 years of experience.

Degrees/Certifications Required: Bachelor's Degree in Computer Science.

Interview Process:

• How many rounds of interviews? 2 Interviews.

• Mid-Senior level.

• Contract.

• Industries: IT Services and IT Consulting.