Semiconductor Memory circuit layout engineer

Semiconductor Memory circuit layout engineer

Tek Wissen provides a unique portfolio of innovative capabilities that seamlessly combines clients insights, strategy, design, software engineering, and systems integration.

The position is for 1 semiconductor memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team.

The chosen candidate should have a minimum of 5-10 years of memory industry design experience.

• Full chip integration for memory chips and Array Diagnostic Monitors (ADM's)
• Full chip DRC and LVS verification
• Definition of full chip signal routing methodology
• Definition of full chip voltage grids and power distribution
• Establishing voltage/reference decoupling cap methodologies that work with signal, power, and fill requirements
• Defining floor plans of entire chips as well as subsystems

• Expert layout of semiconductor logic, analogy, and hierarchical systems.
• Mastery of industry standard physical design and layout tools such as Cadence and Virtuoso.
• Ability to run design checking software, e.g. DRC, LVS.
• Strong verbal and written communication skills.
• Must be able to work in close, team oriented research environment.