Research Engineer II- Semiconductor Fabrication and Advanced Packaging

Job Title

Research Engineer II – Cleanroom Facilities

Atlanta, GA

The Research Engineer II will support and lead semiconductor fabrication, advanced packaging, and heterogeneous integration activities within the IMS Cleanroom Facilities. This role involves hands‑on process development, tool ownership, and research execution across TSV/TGV processing, electroplating, wafer thinning, planarization, CMP, and MEMS/sensor fabrication in a multi‑user research environment.

The position supports collaborative research initiatives involving materials development, interconnect technologies, high‑density integration, and system‑level packaging solutions for next‑generation electronic and sensor platforms.

• Support heterogeneous integration research through materials selection, interconnect process development, and multi‑layer device integration.
• Develop and optimize process flows for TSV/TGV fabrication, copper electroplating and RDL formation, wafer thinning (grinding), planarization and CMP, advanced packaging integration, and MEMS/sensor fabrication.
• Design and execute experimental studies, analyze process data, and establish stable, documented baselines to ensure reproducibility and reliability.
• Serve as technical owner for fabrication and packaging tools (e.g., DRIE/ICP systems, electroplating systems, grinding and CMP tools, and thin‑film deposition systems).
• Train and support academic and industry users on cleanroom processes and equipment.
• Troubleshoot process and equipment issues and coordinate maintenance and continuous improvement efforts.
• Collaborate with faculty, students, and industry partners on prototype development, sponsored research activities, and technical deliverables.

• A master’s degree in science, engineering or related area, and three (3) years of relevant full‑time experience after completion of that degree, or
• A master’s degree in science, engineering or related area, and five (5) years of relevant full‑time experience after completion of a bachelor’s degree, or
• Doctoral degree

• Master's degree or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field.
• Experience in semiconductor fabrication and advanced packaging process development.
• Hands‑on expertise in several of the following areas: DRIE/ICP etching, thin‑film deposition (ALD/PVD/CVD), electroplating, TSV/TGV processing, wafer thinning, planarization, CMP, or packaging assembly.
• Experience with high‑aspect‑ratio via processing and copper fill optimization.
• Background in heterogeneous integration or wafer‑level packaging.
• Experience in MEMS or sensor fabrication.
• Prior experience in an academic cleanroom or semiconductor R&D environment.
• Demonstrated ability to support research projects and contribute to technical documentation, reports, or publications.

Please list 3 professional references.

For additional information about this job opening, please contact Cecelia Jones, Cecelia.jones

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Georgia Tech has policies to promote a healthy work‑life balance and is aware that attracting faculty may require meeting the needs of two careers.

Georgia Tech is a top‑ranked public research university situated in the heart of Atlanta, a diverse and vibrant city with numerous economic and cultural strengths. The Institute serves more than 45,000 students through top‑ranked undergraduate, graduate, and executive programs in engineering, computing, science, business, design, and liberal arts. Georgia Tech's faculty attracted more than $1.4 billion in research awards this past year…