Digital Senior Design Engineer

They gather information about your interactions on the site, such as which pages you visit frequently, how long you stay, and the links or buttons you click. They help us record any difficulties you have with the website and help us to evaluate the effectiveness of our advertising.  By analyzing this data, we can understand what aspects of our site are effective and identify areas for improvement.
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* This is a secondary processing purpose.

Digital Senior Design Engineer page is loaded## Digital Senior Design Engineer locations:
Atlanta time type:
Full time posted on:
Publié aujourd'huijob requisition :
R030555

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
** How You Will Contribute:
** The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects.

Your role as a senior digital design engineer will be to propose innovative solutions, in order to design power and area optimized functional blocks for the Wavelogic family of products.
* As a senior digital design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
* You will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable
* You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions
* You are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification
* You will assist the verification team in determining coverage and provide design assertions and waivers as needed
* You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
* You will be involved in lab validation of the product and its prototype if applicable
* You are expected to report on status updates on a regular basis
** The Must Haves:**
* ** Electrical or computer engineering, or other applicable scientific degree at the BEng/BSc or MEng/MSc level**
* ** Proficiency above the intermediate level with use of System Verilog for design
*** A highly motivated self-starter, able to work independently, while being a team player
* Ability to methodically solve complex technical problems
* Excellent organization, written and oral (English) communication skills
* Familiarity with digital (including formal) verification methods
* Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing
* Good understanding of timing/power/area analysis and trade-offs
** Assets:*
* * Experience with digital silicon design backend process
* Experience with digital design for low power
* Experience with standards and protocols such as
** OTN/FlexO/B100G, Ethernet (100GE+)
*** Experience with using
** GIT for source code management and revision tracking
*** Experience with using
** Jira for schedule planning, assignment tracking and bug reporting
*** Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, System CThe annual pay range for this position  $119,900 - $191,500 USDPay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions,…