ASIC Digital Backend Physical Implementation Engineer

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ASIC Digital Backend Physical Implementation Engineer page is loaded## ASIC Digital Backend Physical Implementation Engineer locations:
Atlanta time type:
Full time posted on:
Publié aujourd'huijob requisition :
R030557

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
** How You Will Contribute:
** Ciena’s Wave Logic family of products is a cornerstone of our optical fiber transmission solutions, driving innovation and success in the telecommunications industry. As a Digital ASIC Physical Implementation Engineer, you will play a critical role in developing large mixed-signal SoC ASICs targeting advanced technology nodes. Your contributions will directly impact the performance, power efficiency, and area optimization of our industry-leading Wave Logic  this role, you will:
* Scope and define the physical architecture of designs, utilizing EDA vendor tools to build, adapt, and maintain a robust flow from netlist to full closure and GDSII generation.
* Partner with RTL circuit designers and other layout engineers to create optimal floor plans, design power grids, and clock distribution networks that achieve the best performance and power efficiency.
* Navigate and fine-tune EDA tool settings, parameters, and attributes to ensure signoff-quality results with an optimal balance of performance, power, and area (PPA).
* Identify and propose alternative implementations, trade-offs, and solutions to achieve lower power consumption and higher performance.
* Collaborate with analog designers and ASIC/SoC teams to integrate analog blocks seamlessly into the overall design.
* Conduct initial Place & Route trials to refine design and correlation, influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable physical design.
* Generate and implement timing ECOs to achieve timing closure, as well as functional ECOs to address RTL feature fixes when necessary.
* Utilize tools like Formality or Conformal for formal verification, analyzing reports and ensuring design accuracy and integrity.
* Write scripts to enhance productivity and efficiency for yourself and other backend engineers. Collaborate with tool and technology vendors to drive fixes, improve workflows, and evaluate new tools and features.
* Produce concise status reports at various stages of development, highlighting trade-offs and providing actionable insights.
* Understand and implement Design for Test (DFT) requirements provided by the ASIC service provider. Use physical-aware synthesis features to mitigate timing issues associated with layout and/or  ECOs.
* Resolve timing challenges associated with DFT through scan chain reordering, placement, and CTS constraints.
* Run Static Timing Analysis (STA), analyze timing reports, and debug issues related to timing constraints, missing exceptions, and tool correlation between P&R and STA tools, ect.
* Your expertise in physical design, collaboration with cross-functional teams, and ability to innovate will be instrumental in advancing Ciena’s cutting-edge optical networking solutions.
* The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to…