Hardware Engineer

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next generation of custom ASICs that power our trading infrastructure.

As a member of the Global Hardware organization, you’ll work on long‑term, high‑impact engineering challenges that directly influence the performance and scalability of IMC’s trading systems. This team focuses on designing proprietary hardware solutions that deliver meaningful advantages in latency‑sensitive environments, partnering closely with software engineers, researchers, and trading teams to solve complex technical problems.

This role combines hardware design, verification, and system‑level thinking. You’ll contribute across the ASIC development lifecycle, from RTL design and validation to integration within larger hardware platforms. Because of the team’s size and collaborative culture, engineers have broad ownership and exposure to multiple aspects of the design process rather than being confined to a narrow specialization.

• Participate in the full ASIC development lifecycle, from specification through integration and deployment
• Design and implement RTL for next‑generation ASIC platforms using System Verilog
• Contribute to architecture and design discussions for performance‑critical hardware systems
• Develop new functionality that supports evolving trading and infrastructure requirements
• Collaborate with hardware, software, and research teams to translate requirements into scalable solutions

• Develop unit tests and verification environments for RTL designs
• Validate functionality and performance of hardware components
• Debug design and integration issues throughout the development process
• Contribute to verification methodologies and testing infrastructure
• Ensure designs meet reliability, performance, and maintainability requirements

• Develop scripts and tooling to improve engineering workflows
• Support automation efforts across design and verification processes
• Contribute to continuous improvements in development methodologies and engineering practices

• BS+ in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
• Strong experience with RTL design and development using System Verilog
• Strong understanding of digital design fundamentals
• Working knowledge of C++
• Experience developing and executing verification and test strategies
• Experience working with multi‑clock‑domain designs and clock‑domain crossing concepts
• Solid understanding of Ethernet protocols and networking fundamentals
• Experience with Python, Bash, or similar scripting languages
• Strong debugging and problem‑solving skills
• Ability to collaborate effectively across multiple engineering disciplines

• ASIC development experience
• FPGA development experience with relevant ASIC design exposure
• Familiarity with PMA (Physical Media Attachment) technologies
• Experience with high‑performance networking systems
• Experience designing low‑latency or performance‑sensitive systems
• Exposure to trading, market infrastructure, or financial technology environments
• Experience building verification frameworks or test automation tools
• Strong C++ development skills

• Balances architecture‑level thinking with hands‑on implementation
• Enjoys solving difficult technical problems across hardware and software domains
• Takes ownership of systems and follows through from design to deployment
• Demonstrates strong attention to detail and engineering rigor
• Thrives in collaborative environments and works well across teams
• Learns quickly and adapts to evolving technical challenges
• Communicates clearly and effectively with both technical and non‑technical stakeholders

$200,000 - $225,000 USD