Senior STA Lead Engineer – ASIC Timing & Power
Listed on 2026-10-03
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Engineering
Electronics Engineer, Hardware Engineer
Samsung Semiconductor India Research (SSIR) seeks an experienced ASIC Design Engineer to lead a team focused on synthesis, timing closure, and low power optimization for high-speed chips. The role involves coordinating with RTL, physical design, and cross-functional teams.
The candidate should bring 12+ years in EE, strong scripting skills (Perl/Tcl), and deep knowledge of Synthesis, DCT/DCG, and constraints-driven design. Bangalore-based, on-site roles.
This posting is for the Senior STA Lead Engineer – ASIC Timing & Power role at Samsung Electronics, based in United States.
This is a strong opening to take on the Senior STA Lead Engineer – ASIC Timing & Power role at Samsung Electronics.
As a Senior STA Lead Engineer – ASIC Timing & Power, you will play an important part at Samsung Electronics in United States.
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